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publication# 11408 rev. e amendment /0 issue date: may 1995 2-126 advanced micro devices am27c4096 4 megabit (262,144 x 16-bit) cmos eprom final distinctive characteristics n fast access time 90 ns n low power consumption 100 m a maximum cmos standby current n jedec-approved pinout plug in upgrade of 1 mbit and 2 mbit eproms 40-pin dip/pdip 44-pin plcc n single + 5 v power supply n 10% power supply tolerance standard on most speeds n 100% flashrite programming typical programming time of 32 seconds n latch-up protected to 100 ma from C1 v to v cc + 1 v n high noise immunity general description the am27c4096 is a 4 mbit ultraviolet erasable pro- grammable read-only memory. it is organized as 256k words by 16 bits per word, operates from a single +5 v supply, has a static standby mode, and features fast sin- gle address location programming. the am27c4096 is ideal for use in 16-bit microprocessor systems. products are available in windowed ceramic dip packages as well as plastic one time programmable (otp) pdip and plcc packages. typically, any byte can be accessed in less than 90 ns, allowing operation with high-performance microproces- sors without any wait states. the am27c4096 offers separate output enable ( oe ) and chip enable ( ce ) controls, thus eliminating bus contention in a multiple bus microprocessor system. amds cmos process technology provides high speed, low power, and high noise immunity. typical power con- sumption is only 125 mw in active mode, and 125 m w in standby mode. all signals are ttl levels, including programming signals. bit locations may be programmed singly, in blocks, or at random. the am27c4096 supports amds flashrite programming algorithm (100 m s pulses) result- ing in typical programming times of 32 seconds. block diagram 11408e-1 v cc v pp oe ce / pgm output enable chip enable and prog logic x decoder y decoder output buffers y gating 4.194,304-bit cell matrix a0Ca17 address inputs data outputs dq0Cdq15 v ss
amd 2-127 am27c4096 product selector guide family part no. ordering part no: v cc + 5% -95 -105 -255 v cc + 10% -100 -120 -150 -200 max access time (ns) 90 100 120 150 200 250 ce ( e ) access time (ns) 90 100 120 150 200 250 oe ( g ) access time (ns) 50 50 50 65 75 75 am27c4096 connection diagrams top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v pp ce ( e )/ pgm ( p ) dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 v ss dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 oe ( g ) v cc a15 a14 a13 a12 a11 a10 a9 v ss a8 a7 a6 a5 a4 a3 a2 a1 a0 11408e-2 dip plcc note: 1. jedec nomenclature is in parentheses. a17 a16 1 44 43 42 5 4 3 2 641 40 7 8 9 10 11 12 13 14 15 16 17 23 24 25 26 19 20 21 22 18 27 28 39 38 37 36 35 34 33 32 31 30 29 dq12 dq11 dq10 dq9 dq8 v ss nc dq7 dq6 dq5 dq4 a13 a12 a11 a10 a9 v ss nc a8 a7 a6 a5 dq13 dq14 dq15 ce ( e )/ pgm ( p ) v pp du v cc a17 a16 a15 a14 dq3 dq2 dq1 dq0 oe ( g ) du a0 a1 a2 a3 a4 11408e-3 11408e-4 pin designations a0C a17 = address inputs ce ( e )/ pgm ( p ) = chip enable input dq0Cdq15 = data input/outputs du = no external connection nc = no internal connection oe ( g ) = output enable input v cc =v cc supply voltage v pp = program voltage input v ss = ground logic symbol a0Ca17 ce ( e )/ pgm oe ( g ) 16 dq0Cdq15 18
amd 2-128 am27c4096 ordering information uv eprom products am27c4096-95 am27c4096-100 am27c4096-105 am27c4096-120 am27c4096-150 am27c4096-200 am27c4096-255 amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: temperature range c = commercial (0 c to +70 c) i = industrial (C40 c to +85 c) e = extended commercial (C55 c to +125 c) package type d = 40-pin ceramic dip (cdv040) speed option see product selector guide and valid combinations device number/description am27c4096 4 megabit (262,144 x 16 bit) cmos uv eprom am27c4096 -95 d c valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the lo- cal amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. valid combinations optional processing blank = standard processing b = burn-in b dc, dcb, de, deb, di, dib dc, dcb, di, dib dc, dcb dc, dcb, di, dib
amd 2-129 am27c4096 ordering information otp products am27c4096-105 am27c4096-120 am27c4096-150 am27c4096-200 am27c4096-255 amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: temperature range c = commercial (0 c to +70 c) i = industrial (C40 c to +85 c) package type p = 40-pin plastic dip (pd 040) j = 44-pin rectangular plastic leaded chip carrier (pl 044) speed option see product selector guide and valid combinations device number/description am27c4096 4 megabit (262,144 x 16 bit ) cmos otp eprom am27c4096 -105 p c valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the lo- cal amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. valid combinations optional processing blank = standard processing pc, jc, pi, ji pc, jc
amd 2-130 am27c4096 functional description erasing the am27c4096 in order to clear all locations of their programmed con- tents, it is necessary to expose the am27c4096 to an ul- traviolet light source. a dosage of 15 w seconds/cm 2 is required to completely erase an am27c4096. this dos- age can be obtained by exposure to an ultraviolet lamp wavelength of 2537 a with intensity of 12,000 m w/ cm 2 for 15 to 20 minutes. the am27c4096 should be di- rectly under and about one inch from the source and all filters should be removed from the uv light source prior to erasure. it is important to note that the am27c4096 and similar devices will erase with light sources having wavelengths shorter than 4000 a . although erasure times will be much longer than with uv sources at 2537 a , exposure to fluorescent light and sunlight will eventually erase the am27c4096 and exposure to them should be prevented to realize maximum system reliability. if used in such an environment, the package window should be covered by an opaque label or substance. programming the am27c4096 upon delivery or after each erasure the am27c4096 has all 4,194,304 bits in the one or high state. zeros are loaded into the am27c4096 through the procedure of programming. the programming mode is entered when 12.75 v 0.25 v is applied to the v pp pin, ce / pgm is at v il and oe is at v ih . for programming, the data to be programmed is applied 16 bits in parallel to the data output pins. the flashrite algorithm reduces programming time by using 100 m s programming pulses and by giving each address only as many pulses as are necessary in order to reliably program the data. after each pulse is applied to a given address, the data in that address is verified. if the data does not verify, additional pulses are given until it verifies or the maximum is reached. this process is repeated while sequencing through each address of the am27c4096. this part of the algorithm is done at v cc = 6.25 v to assure that each eprom bit is programmed to a sufficiently high threshold voltage after the final address is completed, the entire eprom memory is verified at v cc = v pp = 5.25 v. please refer to section 6 for programming flow chart and characteristics. program inhibit programming of multiple am27c4096 in parallel with different data is also easily accomplished. except for ce / pgm , all like inputs of the parallel am27c4096 may be common. a ttl low-level program pulse applied to an am27c4096 ce / pgm input with v pp = 12.75 v 0.25 v and oe high will program that am27c4096. a high-level ce / pgm input inhibits the other am27c4096 devices from being programmed. program verify a verify should be performed on the programmed bits to determine that they were correctly programmed. the verify should be performed with oe at v il , ce / pgm at v ih , and v pp between 12.5 v and 13.0 v. auto select mode the auto select mode allows the reading out of a binary code from an eprom that will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional in the 25 c 5 c ambient temperature range that is required when programming the am27c4096. to activate this mode, the programming equipment must force 12.0 v 0.5 v on address line a9 of the am27c4096. two identifier bytes may then be sequenced from the device outputs by toggling address line a0 from v il to v ih . all other address lines must be held at v il during auto select mode. byte 0 (a0 = v il ) represents the manufacturer code, and byte 1(a0 = v ih ), the device identifier code. for the am27c4096, these two identifier bytes are given in the mode select table. all identifiers for manufacturer and device codes will possess odd parity, with the msb (dq7) defined as the parity bit. read mode the am27c4096 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. chip enable ( ce / pgm ) is the power con- trol and should be used for device selection. output en- able ( oe ) is the output control and should be used to gate data to the output pins, independent of device se- lection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce / pgm to output (t ce ). data is available at the outputs t oe after the falling edge of oe , assuming that ce / pgm has been low and addresses have been stable for at least t acc C t oe . standby mode the am27c4096 has a cmos standby mode which reduces the maximum v cc current to 100 m a. it is placed in cmos-standby when ce / pgm is at v cc 0.3 v. the am27c4096 also has a ttl-standby mode which reduces the maximum v cc current to 1.0 ma. it is placed in ttl-standby when ce / pgm is at v ih . when in standby mode, the outputs are in a high-impedance state, independent of the oe input.
amd 2-131 am27c4096 output or-tieing to accommodate multiple memory connections, a two- line control function is provided to allow for: low memory power dissipation assurance that output bus contention will not occur it is recommended that ce / pgm be decoded and used as the primary device-selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in low-power standby mode and that the output pins are only active when data is desired from a particular memory device. system applications during the switch between active and standby condi- tions, transient current peaks are produced on the rising and falling edges of chip enable. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. at a minimum, a 0.1- m f ceramic capacitor (high frequency, low inher- ent inductance) should be used on each device between v cc and v ss to minimize transient effects. in addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on eprom arrays, a 4.7- m f bulk electrolytic capacitor should be used between v cc and v ss for each eight devices. the location of the capacitor should be close to where the power supply is connected to the array. mode select table mode ce / pgm oe a0 a9 v pp outputs read v il v il xxxd out output disable v il v ih x x x high z standby (ttl) v ih xxxx high z standby (cmos) v cc 0.3 v xxxx high z program v il v ih xxv pp d in program verify v ih v il xxv pp d out program inhibit v ih xxxv pp high z manufacturer code v il v il v il v h x o1h device code v il v il v ih v h x 19h notes: 1. v h = 12.0 v 0.5 v. 2. x = either v ih or v il . 3. a1Ca8 = a10Ca17 = v il . 4. see dc programming characteristics for v pp voltage during programming. pins auto select (note 3)
amd 2-132 am27c4096 absolute maximum ratings storage temperature: otp products C65 c to +125 c . . . . . . . . . . . . . . . . . all other products C65 c to +150 c . . . . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . voltage with respect to v ss : all pins except a9, v pp , and v cc (note 1) C0.6 v to v cc + 0.6 v . . . . . . . . . . a9 and v pp (note 2) C0.6 v to 13.5 v . . . . . . . . . . . . . v cc C0.6 v to 7.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: 1. during transitions, the inputs may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input and i/o may overshoot to v cc + 2.0 v for periods of up to 20 ns. 2. during transitions, a9 and v pp may overshoot v ss to C2.0 v for periods of up to 20 ns. a9 and v pp must not ex- ceed 13.5 v for any period of time. stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a )0 c to +70 c . . . . . . . . . . industrial (i) devices ambient temperature (t a ) C40 c to +85 c . . . . . . . . extended commercial (e) devices ambient temperature (t a ) C55 c to +125 c . . . . . . . supply read voltages: v cc for am27c4096-xx5 +4.75 v to +5.25 v . . . . . . . v cc for am27c4096-xx0 +4.50 v to +5.50 v . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed.
amd 2-133 am27c4096 dc characteristics over operating range unless otherwise specified (notes 1, 2 and 4) parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C400 m a 2.4 v v ol output low voltage i ol = 2.1 ma 0.45 v v ih input high voltage 2.0 v cc +0.5 v v il input low voltage C0.5 +0.8 v i li input load current v in = 0 v to v cc 1.0 m a i lo output leakage current v out = 0 v to v cc 5.0 m a i cc1 v cc active current ce = v il , f = 5 mhz c/i devices 50 (note 3) i out = 0 ma e devices 60 i cc2 v cc ttl standby ce = v ih 1.0 ma i cc3 v cc cmos standby ce = v cc 0.3 v 100 m a i pp1 v pp current during read ce = oe = v il , v pp = v cc 100 m a notes: 1. v cc must be simultaneously or before v pp , and removed simultaneously or after v pp . 2. caution: the am27c4096 must not be removed from (or inserted into) a socket when v cc or v pp is applied. 3. i cc1 is tested with oe = v ih to simulate open outputs. 4. minimum dc input voltage is C0.5 v during transitions, the inputs may overshoot C2.0 v for periods less than 20 ns. maximum dc voltage on output pins is v cc +0.5 v, which may overshoot to v cc +2.0 v for periods less than 20 ns. ma C75 C50 C25 0 25 50 75 100 125 150 30 28 26 24 22 frequency in mhz 11408e-5 12345678910 35 30 25 20 15 supply current in ma supply current in ma temperature in c figure 1. typical supply current vs. frequency v cc = 5.5 v, t = 25 c figure 2. typical supply current vs. temperature v cc = 5.5 v, f = 5 mhz 11408e-6
amd 2-134 am27c4096 capacitance parameter parameter symbol description test conditions typ max typ max typ max unit c in input capacitance v in = 0 v 10 13 6 8 10 13 pf c out output capacitance v out = 0 v 10 13 8 10 12 14 pf notes: 1. this parameter is only sampled and not 100% tested. 2. t a = +25 c, f = 1 mhz. cdv040 pd040 pl044 switching characteristics over operating range unless otherwise specified (notes 1, 3 and 4) jedec standard parameter description test conditions -95 -105 -120 -150 -200 -255 unit a vqv t acc address to ce = oe = v il min output delay max 90 100 120 150 200 250 t elqv t ce chip enable to oe = v il min output delay max 90 100 120 150 200 250 t glqv t oe output enable to ce = v il min output delay max 50 50 50 65 75 75 t ehqz ,t df min t ghqz (note 2) max 30 30 40 40 40 60 t axqx t oh min00000 0 max parameter symbols am27c4096 chip enable high or output enable high, whichever comes first, to output float ns ns ns ns ns notes: 1. v cc must be applied simultaneously or before v pp, and removed simultaneously or after v pp . 2. this parameter is only sampled and not 100% tested. 3. caution: the am27c4096 must not be removed from (or inserted into) a socket or board when v pp or v cc is applied. 4. output load: 1 ttl gate and c l = 100 pf input rise and fall times: 20 ns input pulse levels: 0.45 v to 2.4 v timing measurement reference level: 0.8 v and 2 v inputs and outputs. output hold from addresses, ce, or oe, whichever occurred first
amd 2-135 am27c4096 switching test circuit 11408e-7 device under test 5.0 v diodes = in3064 or equivalent c l 6.2 k w 2.7 k w c l = 100 pf including jig capacitance switching test waveform 11408e-8 ac testing: inputs are driven at 2.4 v for a logic 1 and 0.45 v for a logic 0. input pulse rise and fall times are 20 ns. 2.4 v 0.45 v 2.0 v 0.8 v test points 2.0 v 0.8 v input output
amd 2-136 am27c4096 key to switching waveforms ks000010 must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs switching waveform addresses ce / pgm oe output addresses valid high z high z t ce valid output 2.4 0.45 2.0 0.8 2.0 0.8 t acc (note 1) t oe t df (note 2) t oh notes: 1. oe may be delayed up to t acc C t oe after the falling edge of the addresses without impact on t acc. 2. t df is specified from oe or ce , whichever occurs first. 11408e-9

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